
Bengaluru, Hyderabad · Hybrid
ASIC Design Engineer, BOOT and Power Management
- Salary
- Not disclosed
- Experience
- 2–6 years
- Eligible batches
- 2020 – 2024
- Degree
- B.Tech, M.Tech
- Location
- Bengaluru, HyderabadHybrid
About the role
NVIDIA is seeking an ASIC Design Engineer to lead the BOOT and Power Management subsystem for automotive and client chips. The role involves creating micro‑architectures, writing RTL, and collaborating across hardware, verification, timing and physical design teams.
Responsibilities
- Define and own micro‑architecture and RTL for BOOT and power modules.
- Balance performance, power and area targets while making architectural trade‑offs.
- Partner with hardware architects to specify critical features.
- Coordinate with verification teams to ensure functional correctness.
- Work with timing, VLSI and physical design groups to meet timing and routing constraints.
Eligibility
- B.Tech or M.Tech degree.
- Minimum 2 years of experience designing complex ASIC units or CPU‑based subsystems.
- Strong debugging, analytical and problem‑solving abilities.
- Excellent influencing and teamwork skills across multicultural, multi‑geography teams.
Skills
Resume keywords
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Asked for
- RTL
- Micro-architecture
- Verification
- Timing
- VLSI
- Physical design
- Debugging
Nice to have
- Security
- Protocols
- System security
Benefits
- Competitive salary package.
- Comprehensive health and family benefits.
- Access to NVIDIA’s learning and development resources.
- Inclusive and diverse work environment.
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About NVIDIA
Designs GPUs, networking and CUDA software for AI in data centres, plus GeForce gaming graphics, RTX professional graphics and chips for cars.
Founded 1993 · 5000+ employees · HQ Santa Clara, California, United States
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