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Bengaluru · Hybrid

ASIC Design Engineer - Performance Monitoring

Full-timePosted
Salary
₹5.1–7.4 LPAEstimated from AmbitionBox
Experience
3–6 years
Eligible batches
2020 – 2023
Degree
B.Tech, M.Tech
Location
BengaluruHybrid

About the role

NVIDIA's System‑On‑Chip group seeks an ASIC Design Engineer to drive RTL design and performance‑monitoring methodologies for cutting‑edge GPUs and SOCs. The position is based in Bengaluru and operates in a hybrid work model.

Responsibilities

  • Define and develop system‑level RTL and associated methodologies for performance measurement.
  • Design, implement, and take RTL features through the full SOC design cycle.
  • Run and debug RTL checks such as CDC, RDC, lint, synthesis, and logic‑equivalence.
  • Create and automate flows that streamline system‑level IP development.
  • Collaborate with architects, verification, and software engineers to deliver tasks.

Eligibility

  • B.Tech or M.Tech in Electronics or Computer Engineering.
  • Minimum of 3 years of relevant industry experience.
  • Strong communication and teamwork abilities.

Skills

  • Proficiency in Verilog‑based RTL design.
  • Experience with SOC design/implementation flows and automation.
  • Solid coding skills in Perl, Python, or similar scripting languages.
  • Familiarity with synthesis (dc_shell) and simulation (VCS) tools.
  • Ability to use debugging tools such as Debussy or GDB.
  • Comfort with AI‑assisted productivity tools.

Resume keywords

Asked for

  • Verilog
  • Perl
  • Python
  • RTL
  • Soc
  • Dc_shell
  • Vcs
  • Debugging

Nice to have

  • AI
Tailor my resume with these

Benefits

  • Opportunity to work on industry‑leading GPU/SOC projects.
  • Collaborative environment with cross‑functional teams.
  • Access to cutting‑edge AI tools for design automation.
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About NVIDIA

Designs GPUs, networking and CUDA software for AI in data centres, plus GeForce gaming graphics, RTX professional graphics and chips for cars.

Founded 1993 · 5000+ employees · HQ Santa Clara, California, United States

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