System Validation Engineer (New Grad)

About the role

SiFive is looking for fresh engineering graduates to join its System Validation team. The role focuses on validating RISC‑V CPUs using FPGA platforms, development boards and bring‑up environments, providing hands‑on experience with hardware‑software debugging and processor architecture.

Responsibilities

• Validate RISC‑V processors and related hardware on FPGA‑based platforms.
• Perform root‑cause analysis of hardware and software failures.
• Use ILA and JTAG tools to debug and troubleshoot FPGA designs.
• Develop and maintain Python and Bash scripts to automate validation workflows.
• Support board bring‑up activities and document validation results.

Eligibility

• Bachelor’s or Master’s degree in Computer Science or Electronics & Communication Engineering.
• Strong understanding of computer architecture and logic design.
• Practical exposure to Verilog and FPGA development.
• Experience with Linux and scripting in Python/Bash.
• Positive attitude, willingness to learn and high‑quality engineering mindset.

Skills

• Computer architecture concepts.
• Digital logic design and Verilog.
• FPGA synthesis, programming and validation.
• Linux operating system proficiency.
• Scripting in Python and Bash.
• Debugging using ILA and JTAG.